1. Field of the Invention
The present invention relates generally to electrical circuits and, more particularly, to programmable logic circuits and methods.
2. Related Art
Programmable logic devices (PLDs) are well known in the electronic art and are commonly used to implement Boolean logic functions. There exists a wide variety of PLD techniques including programmable logic arrays (PLAs), programmable array logic (PAL), field programmable logic arrays (FPLAs), and electrically erasable programmable logic devices (EEPLDs), to name but a few.
Traditionally, PLDs have used sense amplifiers (e.g., to sense the data in a memory matrix) to provide the output signals of programmable logic operations (e.g., a logical AND operation) of many inputs. For semiconductor processes of 0.25 xcexcm and 2.5 V, the sense amplifier generally provided the best solution, at the cost of requiring additional power, because the ring oscillator speeds were relatively slow, the pertinent design rules were lax, and sufficient space existed for the sense amplifiers. However, integrated circuit technology and semiconductor processing have continued to make significant advances. For example, the operating characteristics, such as lower power consumption, superior voltage and current attributes, and scaling have improved. In a sense amplifier, however, it is difficult to scale the sense transistor, because of reliability concerns. The speed of the sense amplifier has shown little improvement over time also. Furthermore, the power requirements of the sense amplifier have become significant relative to other components.
The programmable logic systems and methods of the present invention provide increased speed and lower power dissipation, while providing a size that scales with semiconductor processing requirements. In accordance with an embodiment of the present invention, the wide input programmable logic system utilizes complementary metal-oxide semiconductor (CMOS) gates to provide the output signals. In accordance with another embodiment of the present invention, an electrically erasable programmable non-volatile memory cell is disclosed that provides a zero-power memory cell, achieved through certain signal timing and pre-charging.
In accordance with an embodiment of the present invention, a wide-input programmable logic system includes a plurality of complex CMOS logic gates that perform a logical sequence including at least one of a NOR-NAND and a NAND-NOR to generate a final output term, which is a product of the inputs (e.g., row driver signals).
In accordance with another embodiment of the present invention, an electrically erasable non-volatile memory cell is provided that includes a storage cell that stores a logical value and a select transistor coupled to the storage cell. The select transistor is controlled by a first control signal, with the select transistor isolating the storage cell during editing upon receipt of an asserted state of the first control signal. A latch is coupled to the select transistor and controlled by a latch control signal to provide an output corresponding to the logical value stored in the storage cell. Respective timing of the first control signal and the latch control signal results in zero power dissipated by the electrically erasable non-volatile memory cell.